//------------------------------------------------------------------------------
// Copyright 2012 (c) Silicon Laboratories Inc.
//
// SPDX-License-Identifier: Zlib
//
// This siHAL software is provided 'as-is', without any express or implied
// warranty. In no event will the authors be held liable for any damages
// arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it
// freely, subject to the following restrictions:
//
// 1. The origin of this software must not be misrepresented; you must not
//    claim that you wrote the original software. If you use this software
//    in a product, an acknowledgment in the product documentation would be
//    appreciated but is not required.
// 2. Altered source versions must be plainly marked as such, and must not be
//    misrepresented as being the original software.
// 3. This notice may not be removed or altered from any source distribution.
//------------------------------------------------------------------------------
//
// This file applies to the SIM3U1XX_DMAXBAR_A module
//
// Script: 0.57
// Version: 1

#ifndef __SI32_DMAXBAR_A_REGISTERS_H__
#define __SI32_DMAXBAR_A_REGISTERS_H__

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

struct SI32_DMAXBAR_A_DMAXBAR0_Struct
{
   union
   {
      struct
      {
         // DMA Channel 0 Peripheral Select
         volatile uint32_t CH0SEL: 4;
         // DMA Channel 1 Peripheral Select
         volatile uint32_t CH1SEL: 4;
         // DMA Channel 2 Peripheral Select
         volatile uint32_t CH2SEL: 4;
         // DMA Channel 3 Peripheral Select
         volatile uint32_t CH3SEL: 4;
         // DMA Channel 4 Peripheral Select
         volatile uint32_t CH4SEL: 4;
         // DMA Channel 5 Peripheral Select
         volatile uint32_t CH5SEL: 4;
         // DMA Channel 6 Peripheral Select
         volatile uint32_t CH6SEL: 4;
         // DMA Channel 7 Peripheral Select
         volatile uint32_t CH7SEL: 4;
      };
      volatile uint32_t U32;
   };
};

#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_MASK  0x0000000F
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT  0
// Service USB0 EP4 OUT data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_USB0_EP4_OUT_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_USB0_EP4_OUT_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_USB0_EP4_OUT_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service SPI1 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SPI1_RX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SPI1_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SPI1_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service USART0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_USART0_RX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_USART0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_USART0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service I2C0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_I2C0_TX_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_I2C0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_I2C0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T0_RISE_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T0_FALL_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T1_RISE_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T1_FALL_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service TIMER0L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER0L_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER0L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER0L_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service TIMER0H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER0H_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER0H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER0H_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service TIMER1L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER1L_VALUE  10
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER1L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER1L_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)
// Service TIMER1H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER1H_VALUE  11
#define SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER1H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_TIMER1H_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH0SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_MASK  0x000000F0
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT  4
// Service USB0 EP3 OUT data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_USB0_EP3_OUT_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_USB0_EP3_OUT_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_USB0_EP3_OUT_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service SPI0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SPI0_RX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SPI0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SPI0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service USART1 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_USART1_RX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_USART1_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_USART1_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service I2C0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_I2C0_RX_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_I2C0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_I2C0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service IDAC1 data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_IDAC1_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_IDAC1_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_IDAC1_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service EPCA0 control data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_EPCA0_CONTROL_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_EPCA0_CONTROL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_EPCA0_CONTROL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T0_RISE_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T0_FALL_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T1_RISE_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T1_FALL_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service TIMER0L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER0L_VALUE  10
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER0L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER0L_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service TIMER1L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER1L_VALUE  11
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER1L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER1L_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)
// Service TIMER1H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER1H_VALUE  12
#define SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER1H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_TIMER1H_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH1SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_MASK  0x00000F00
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT  8
// Service USB0 EP2 OUT data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_USB0_EP2_OUT_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_USB0_EP2_OUT_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_USB0_EP2_OUT_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service SPI0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SPI0_TX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SPI0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SPI0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service USART0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_USART0_TX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_USART0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_USART0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service SARADC0 data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SARADC0_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SARADC0_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SARADC0_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service IDAC1 data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_IDAC1_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_IDAC1_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_IDAC1_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service I2S0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_I2S0_TX_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_I2S0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_I2S0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service EPCA0 control data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_EPCA0_CONTROL_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_EPCA0_CONTROL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_EPCA0_CONTROL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T0_RISE_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T0_FALL_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T1_RISE_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T1_FALL_VALUE  10
#define SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH2SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_MASK  0x0000F000
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT  12
// Service USB0 EP1 OUT data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_USB0_EP1_OUT_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_USB0_EP1_OUT_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_USB0_EP1_OUT_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service SARADC1 data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SARADC1_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SARADC1_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SARADC1_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service IDAC0 data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_IDAC0_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_IDAC0_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_IDAC0_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service I2S0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_I2S0_TX_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_I2S0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_I2S0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service EPCA0 capture data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_EPCA0_CAPTURE_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_EPCA0_CAPTURE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_EPCA0_CAPTURE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T0_RISE_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T0_FALL_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T1_RISE_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T1_FALL_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)
// Service TIMER1H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_TIMER1H_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_TIMER1H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_TIMER1H_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH3SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_MASK  0x000F0000
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT  16
// Service USB0 EP4 IN data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_USB0_EP4_IN_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_USB0_EP4_IN_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_USB0_EP4_IN_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service SPI1 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SPI1_TX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SPI1_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SPI1_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service USART0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_USART0_TX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_USART0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_USART0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service SARADC0 data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SARADC0_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SARADC0_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SARADC0_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service I2S0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_I2S0_RX_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_I2S0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_I2S0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service EPCA0 capture data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_EPCA0_CAPTURE_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_EPCA0_CAPTURE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_EPCA0_CAPTURE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T0_RISE_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T0_FALL_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T1_RISE_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T1_FALL_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)
// Service TIMER0H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_TIMER0H_VALUE  10
#define SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_TIMER0H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_TIMER0H_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH4SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_MASK  0x00F00000
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT  20
// Service USB0 EP3 IN data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_USB0_EP3_IN_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_USB0_EP3_IN_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_USB0_EP3_IN_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)
// Service AES0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_AES0_TX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_AES0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_AES0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)
// Service USART1 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_USART1_TX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_USART1_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_USART1_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)
// Service SARADC0 data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SARADC0_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SARADC0_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SARADC0_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)
// Service I2S0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_I2S0_RX_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_I2S0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_I2S0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T0_RISE_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T0_FALL_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T1_RISE_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T1_FALL_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH5SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_MASK  0x0F000000
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT  24
// Service USB0 EP2 IN data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_USB0_EP2_IN_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_USB0_EP2_IN_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_USB0_EP2_IN_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service AES0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_AES0_RX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_AES0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_AES0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service USART0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_USART0_RX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_USART0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_USART0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service I2C0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_I2C0_RX_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_I2C0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_I2C0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service IDAC0 data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_IDAC0_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_IDAC0_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_IDAC0_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T0_RISE_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T0_FALL_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T1_RISE_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T1_FALL_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)
// Service TIMER0H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_TIMER0H_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_TIMER0H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_TIMER0H_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH6SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_MASK  0xF0000000
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT  28
// Service USB0 EP1 IN data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_USB0_EP1_IN_VALUE  0U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_USB0_EP1_IN_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_USB0_EP1_IN_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service AES0 XOR data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_AES0_XOR_VALUE  1U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_AES0_XOR_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_AES0_XOR_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service SPI1 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SPI1_TX_VALUE  2U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SPI1_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SPI1_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service USART0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_USART0_TX_VALUE  3U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_USART0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_USART0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T0_RISE_VALUE  4U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T0_FALL_VALUE  5U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T1_RISE_VALUE  6U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T1_FALL_VALUE  7U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service TIMER0L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER0L_VALUE  8U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER0L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER0L_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service TIMER1L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER1L_VALUE  9U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER1L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER1L_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)
// Service TIMER1H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER1H_VALUE  10U
#define SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER1H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_TIMER1H_VALUE << SI32_DMAXBAR_A_DMAXBAR0_CH7SEL_SHIFT)



struct SI32_DMAXBAR_A_DMAXBAR1_Struct
{
   union
   {
      struct
      {
         // DMA Channel 8 Peripheral Select
         volatile uint32_t CH8SEL: 4;
         // DMA Channel 9 Peripheral Select
         volatile uint32_t CH9SEL: 4;
         // DMA Channel 10 Peripheral Select
         volatile uint32_t CH10SEL: 4;
         // DMA Channel 11 Peripheral Select
         volatile uint32_t CH11SEL: 4;
         // DMA Channel 12 Peripheral Select
         volatile uint32_t CH12SEL: 4;
         // DMA Channel 13 Peripheral Select
         volatile uint32_t CH13SEL: 4;
         // DMA Channel 14 Peripheral Select
         volatile uint32_t CH14SEL: 4;
         // DMA Channel 15 Peripheral Select
         volatile uint32_t CH15SEL: 4;
      };
      volatile uint32_t U32;
   };
};

#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_MASK  0x0000000F
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT  0
// Service USB0 EP4 OUT data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USB0_EP4_OUT_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USB0_EP4_OUT_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USB0_EP4_OUT_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)
// Service USART1 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USART1_RX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USART1_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USART1_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)
// Service SPI1 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SPI1_RX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SPI1_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SPI1_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)
// Service USART0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USART0_RX_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USART0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_USART0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)
// Service EPCA0 capture data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_EPCA0_CAPTURE_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_EPCA0_CAPTURE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_EPCA0_CAPTURE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T0_RISE_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T0_FALL_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T1_RISE_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T1_FALL_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH8SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_MASK  0x000000F0
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT  4
// Service USB0 EP3 OUT data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_USB0_EP3_OUT_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_USB0_EP3_OUT_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_USB0_EP3_OUT_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)
// Service USART1 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_USART1_TX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_USART1_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_USART1_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)
// Service I2C0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_I2C0_TX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_I2C0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_I2C0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)
// Service EPCA0 capture data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_EPCA0_CAPTURE_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_EPCA0_CAPTURE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_EPCA0_CAPTURE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T0_RISE_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T0_FALL_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T1_RISE_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T1_FALL_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)
// Service TIMER0H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_TIMER0H_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_TIMER0H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_TIMER0H_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH9SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_MASK  0x00000F00
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT  8
// Service USB0 EP2 OUT data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_USB0_EP2_OUT_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_USB0_EP2_OUT_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_USB0_EP2_OUT_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)
// Service AES0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_AES0_TX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_AES0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_AES0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)
// Service SARADC1 data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SARADC1_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SARADC1_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SARADC1_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)
// Service I2S0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_I2S0_RX_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_I2S0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_I2S0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T0_RISE_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T0_FALL_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T1_RISE_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T1_FALL_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)
// Service TIMER1H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_TIMER1H_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_TIMER1H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_TIMER1H_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH10SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_MASK  0x0000F000
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT  12
// Service USB0 EP1 OUT data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USB0_EP1_OUT_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USB0_EP1_OUT_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USB0_EP1_OUT_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service AES0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_AES0_RX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_AES0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_AES0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service USART1 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USART1_RX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USART1_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USART1_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service USART0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USART0_RX_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USART0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_USART0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service I2C0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_I2C0_RX_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_I2C0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_I2C0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service I2S0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_I2S0_RX_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_I2S0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_I2S0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T0_RISE_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T0_FALL_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T1_RISE_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T1_FALL_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)
// Service TIMER0H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_TIMER0H_VALUE  10
#define SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_TIMER0H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_TIMER0H_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH11SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_MASK  0x000F0000
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT  16
// Service USB0 EP4 IN data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_USB0_EP4_IN_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_USB0_EP4_IN_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_USB0_EP4_IN_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service AES0 XOR data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_AES0_XOR_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_AES0_XOR_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_AES0_XOR_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service USART1 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_USART1_TX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_USART1_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_USART1_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service SPI1 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SPI1_TX_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SPI1_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SPI1_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service IDAC1 data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_IDAC1_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_IDAC1_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_IDAC1_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service I2S0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_I2S0_TX_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_I2S0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_I2S0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T0_RISE_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T0_FALL_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T1_RISE_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T1_FALL_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service TIMER0L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER0L_VALUE  10
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER0L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER0L_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service TIMER1L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER1L_VALUE  11
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER1L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER1L_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)
// Service TIMER1H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER1H_VALUE  12
#define SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER1H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_TIMER1H_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH12SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_MASK  0x00F00000
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT  20
// Service USB0 EP3 IN data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_USB0_EP3_IN_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_USB0_EP3_IN_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_USB0_EP3_IN_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service SPI0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SPI0_RX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SPI0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SPI0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service USART0 RX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_USART0_RX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_USART0_RX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_USART0_RX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service IDAC1 data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_IDAC1_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_IDAC1_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_IDAC1_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service I2S0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_I2S0_TX_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_I2S0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_I2S0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T0_RISE_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T0_FALL_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T1_RISE_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T1_FALL_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)
// Service TIMER0H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_TIMER0H_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_TIMER0H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_TIMER0H_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH13SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_MASK  0x0F000000
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT  24
// Service USB0 EP2 IN data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_USB0_EP2_IN_VALUE  0
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_USB0_EP2_IN_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_USB0_EP2_IN_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service SPI0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SPI0_TX_VALUE  1
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SPI0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SPI0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service USART0 TX data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_USART0_TX_VALUE  2
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_USART0_TX_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_USART0_TX_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service IDAC0 data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_IDAC0_VALUE  3
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_IDAC0_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_IDAC0_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service EPCA0 control data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_EPCA0_CONTROL_VALUE  4
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_EPCA0_CONTROL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_EPCA0_CONTROL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T0_RISE_VALUE  5
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T0_FALL_VALUE  6
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T1_RISE_VALUE  7
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T1_FALL_VALUE  8
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service TIMER0L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_TIMER0L_VALUE  9
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_TIMER0L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_TIMER0L_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)
// Service TIMER1L overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_TIMER1L_VALUE  10
#define SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_TIMER1L_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_TIMER1L_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH14SEL_SHIFT)

#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_MASK  0xF0000000
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT  28
// Service USB0 EP1 IN data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_USB0_EP1_IN_VALUE  0U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_USB0_EP1_IN_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_USB0_EP1_IN_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service SARADC1 data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SARADC1_VALUE  1U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SARADC1_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SARADC1_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service IDAC0 data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_IDAC0_VALUE  2U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_IDAC0_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_IDAC0_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service EPCA0 control data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_EPCA0_CONTROL_VALUE  3U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_EPCA0_CONTROL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_EPCA0_CONTROL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service DMAXT0 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T0_RISE_VALUE  4U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T0_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T0_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service DMAXT0 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T0_FALL_VALUE  5U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T0_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T0_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service DMAXT1 rising edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T1_RISE_VALUE  6U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T1_RISE_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T1_RISE_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service DMAXT1 falling edge data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T1_FALL_VALUE  7U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T1_FALL_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_DMA0T1_FALL_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service TIMER0H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_TIMER0H_VALUE  8U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_TIMER0H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_TIMER0H_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)
// Service TIMER1H overflow data requests.
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_TIMER1H_VALUE  9U
#define SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_TIMER1H_U32 \
   (SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_TIMER1H_VALUE << SI32_DMAXBAR_A_DMAXBAR1_CH15SEL_SHIFT)



typedef struct SI32_DMAXBAR_A_Struct
{
   struct SI32_DMAXBAR_A_DMAXBAR0_Struct           DMAXBAR0       ; // Base Address + 0x0
   volatile uint32_t                               DMAXBAR0_SET;
   volatile uint32_t                               DMAXBAR0_CLR;
   uint32_t                                        reserved0;
   struct SI32_DMAXBAR_A_DMAXBAR1_Struct           DMAXBAR1       ; // Base Address + 0x10
   volatile uint32_t                               DMAXBAR1_SET;
   volatile uint32_t                               DMAXBAR1_CLR;
   uint32_t                                        reserved1;
} SI32_DMAXBAR_A_Type;

#ifdef __cplusplus
}
#endif

#endif // __SI32_DMAXBAR_A_REGISTERS_H__

//-eof--------------------------------------------------------------------------

